Semiconductor data storage structures can include volatile circuits, such as latch circuits included in conventional static random access memories (SRAMs). Such latches can include four transistor (4-T) cells and six transistor (6-T) cells, as just two examples. Data storage structures can also include nonvolatile circuits, such as those included in erasable programmable read-only-memories (such EPROMs, conventional EEPROMs, and "flash" EEPROMs). As is well understood, a nonvolatile circuit can retain its stored data in the absence of power. Conversely, volatile circuits will lose stored data in the absence of power.
Typically, conventional volatile circuits may provide a more rapid response than nonvolatile circuits. Thus, memory devices formed with conventional volatile circuits may have faster read times.
Most commercial environments can allow conventional volatile circuits to operate with acceptable reliability. However, some environments, such space and/or high-earth orbit, are not conducive to the reliability of volatile circuit operation. Without the protection of an atmosphere, various events can occur with increased frequency that may disturb the operation of a semiconductor device. Such events can include bursts of gamma radiation and/or single particle events (also referred to as random event upset or single event upset). Such radiation/particles can generate electron-hole pairs within a semiconductor substrate, temporarily injecting current into nodes within the volatile circuits. This may undesirably alter the potential at such circuit nodes. In a bi-stable circuit, like a conventional latch, such a disturb can cause the latch to "flip," and thus store erroneous data.
One approach that may provide both rapid operation and a form of nonvolatility is to modify a conventional latch with nonvolatile elements. Such volatile-nonvolatile hybrid circuits can allow the data stored within the latch to be "programmed." Once programmed, such circuits may be more resistant to disturb events. Further, in the event power is lost, when power is reapplied, the latch will power-up with the programmed data values. Similarly, if erroneous operation occurs due to a radiation/particle induced event, the circuit can be "reset" by removing and then reapplying power to restore correct data values.
One example of a storage circuit that includes volatile and nonvolatile elements is set forth in FIG. 3. FIG. 3 is an eight transistor (8-T) metal-nitride-oxide-semiconductor (MNOS) latch. The 8-T MNOS latch is designated by the general reference character 300, and is shown to have a 6-T volatile latch arrangement with two additional MNOS transistors.
MNOS transistors can include an insulated gate field effect structure having a metal gate separated from a semiconductor substrate by a silicon nitride ("nitride")/silicon dioxide ("oxide") layer. A MNOS transistor can operate in a nonvolatile fashion by trapping charge at the nitride/oxide interface. For example, an MNOS transistor can be "erased" by applying an electric field across the nitride/oxide interface that can result in electrons tunneling from the interface to a substrate and/or "holes" tunneling into the interface. In the case of an n-channel MNOS transistor, such an operation can lower the threshold voltage of the transistor. Conversely, an MNOS transistor can be programmed by applying an opposite electric field across the interface. Electrons can tunnel into the interface and/or holes can tunnel from the interface. In the case of an n-channel MNOS transistor, such an operation can raise the threshold voltage of the transistor.
A drawback to MNOS transistors is that such devices can have a relatively high programming and/or erase voltage. As but one example, the electric field for erasing and programming an MNOS transistor can be +/-15 volts.
Unfortunately, higher voltage semiconductor devices must often include specialized structures. For example, MOS devices must be formed within specialized high voltage wells that can have particular doping profiles, including double and/or triple diffused wells. Further, sources and drains may also be double diffused. Such devices may further include specialized insulating arrangements.
Specialized high-voltage structures may not be readily "scalable." That is, as manufacturing processes improve, conventional devices (such as transistors) are scalable, as they can be shrunk with each new generation. Scalable structures may thus reduce the overall cost in manufacturing a semiconductor device. However, higher-voltage structures, such as those used to program and/or erase MNOS transistors can remain unduly large, adding to the size of the overall device and/or requiring portions that must be customed designed. As just one example, double and triple diffused wells can push out spacing requirements in lateral and/or vertical directions. Such structures may add to the expense and complexity in a manufacturing process.
Further, in the event a higher programming and/or erase voltage is generated "on-chip" more circuit area can be required. As just one example, more charge pump stages may be used to generate a higher programming and/or erase voltage than a lower programming and/or erase voltage.
Referring back to FIG. 3, a conventional 8-T MNOS latch 300 can include an n-channel metal-oxide-semiconductor (NMOS) transistor 302 and a p-channel MOS (PMOS) transistor (PMOS) 304 that form a first pair. A first pair can be cross-coupled with a second pair that includes NMOS transistor 306 and PMOS transistor 308. The gates of NMOS and PMOS transistors 306 and 308 can be commonly coupled to a first data node 310. The gates of NMOS and PMOS transistors 302 and 304 can be commonly coupled to a second data node 312. Data nodes 310 and 312 can be connected to complementary bit lines 314 and 316 by NMOS pass transistors 318 and 320, respectively. The gates of NMOS pass transistors 318 and 320 can be commonly connected to a word line WL. The sources of PMOS transistors 304 and 308 can be commonly connected to a high power supply voltage VCC. The sources of NMOS transistors 302 and 306 can be commonly connected to a low supply voltage VSS (e.g., "grounded").
Unlike a conventional complementary MOS latch circuit, an 8-T MNOS latch may also include an n-channel MNOS transistor 322 having a source-drain path connected between the drains of NMOS transistor 302 and PMOS transistor 304. Another n-channel MNOS transistor 324 can have a source-drain path connected between the drains of NMOS transistor 306 and PMOS transistor 308. The gates of MNOS transistors (322 and 324) can be commonly coupled to a program voltage VP or a high power supply voltage VCC.
A form of nonvolatility can be introduced into the 8-T MNOS latch 300 by programming MNOS transistors (322 and 324) to opposite states. As just one example, MNOS transistor 322 can be programmed to an erased state, while MNOS transistor 324 can be programmed to a programmed state. In such an arrangement, as power is applied to the circuit, an MNOS transistor 322 may have a low impedance path with respect to MNOS transistor 324. Transistor 324 can have a high impedance path with respect to MNOS transistor 322. First data node 310 can rise to the VCC potential while second data node 312 can fall to the VSS potential. Obviously, if MNOS transistor 322 was in a programmed state and MNOS transistor 324 was in an erased state, an 8-T MNOS latch 300 could power-up into the opposite logic state (first data node 310 low, second data node 312 high).
As shown in FIG. 3, the gates of MNOS transistors (322 and 324) can also be connected to a high power supply voltage VCC. This connection can occur in a power-up operation and a read operation. A drawback to such an arrangement is that a field can be formed across the MNOS transistors (322 and 324) that can contribute to charge leakage, and may thus reduce overall data retention time in the MNOS transistors (322 and 324). As just one example, a high power supply voltage VCC on the gate of an erased MNOS transistor can generate a field across the nitride/oxide interface that may assist electron transport to the nitride/oxide interface, thereby undesirably increasing the threshold voltage of the MNOS transistor.
While the arrangement of FIG. 3 describes an 8-T MNOS latch 300 that includes n-channel MNOS devices, such an arrangement can alternatively include p-channel MNOS devices. In a read operation, the gates of p-channel MNOS devices can be coupled to a low power supply voltage VSS. Such a low power supply voltage can also generate a field across the nitride/oxide interface that may reduce data retention times in such p-channel MNOS devices.
In light of the above drawbacks that may be inherent in conventional 8-T MNOS latch circuits, it would be desirable to arrive at a nonvolatile storage structure that can be more compatible with modern scaled process technologies.
It would also be desirable arrive at a nonvolatile storage structure that may improve nonvolatile data retention times.
It would further be desirable arrive at a nonvolatile storage structure that includes nonvolatile elements that may be programmable at a lower voltage than prior art approaches.